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Update README for ascad-v1-fk with dimensions and leakage plots

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@@ -68,6 +68,18 @@ The following targets are available for side-channel leakage analysis on this da
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  | `v1_sbo_masked` | Boolean-masked SBO at byte ``byte_index`` after full maskedSubBytes.<br><br>``SBOX(ptx[i] ^ key[i]) ^ mask[i]`` where ``i = byte_index``.<br><br>State value written back into ``state[i]`` at the end of the inner loop: rout has been removed and only the per-byte mask remains.<br><br>**Replaces:** ``sasca_y0`` from the Bronchain et al. SASCA factor graph. |
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  | `v1_sbo_mid` | Mid-SubBytes state at byte ``byte_index`` before the final rout strip.<br><br>``SBOX(ptx[i] ^ key[i]) ^ rout ^ mask[i]`` where ``i = byte_index``.<br><br>``raw_out ^ masksState[i]`` in the AVR inner loop: the value in the register after XOR-ing the LUT output with the per-byte mask, before the final ``EOR r_val, r1`` removes rout. |
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  ## Parameters Used for Generation
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  - **HF_ORG**: `DLSCA`
 
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  | `v1_sbo_masked` | Boolean-masked SBO at byte ``byte_index`` after full maskedSubBytes.<br><br>``SBOX(ptx[i] ^ key[i]) ^ mask[i]`` where ``i = byte_index``.<br><br>State value written back into ``state[i]`` at the end of the inner loop: rout has been removed and only the per-byte mask remains.<br><br>**Replaces:** ``sasca_y0`` from the Bronchain et al. SASCA factor graph. |
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  | `v1_sbo_mid` | Mid-SubBytes state at byte ``byte_index`` before the final rout strip.<br><br>``SBOX(ptx[i] ^ key[i]) ^ rout ^ mask[i]`` where ``i = byte_index``.<br><br>``raw_out ^ masksState[i]`` in the AVR inner loop: the value in the register after XOR-ing the LUT output with the per-byte mask, before the final ``EOR r_val, r1`` removes rout. |
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+ ## Auto-Generated Leakage Plots
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+
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+ | Dataset | Target | Byte Index | Plot |
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+ | :--- | :--- | :---: | :---: |
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+ | ascad-v1-fk | ciphertext | 0 | <img src="plots/ascad_v1_fk_ciphertext_0.png" alt="ascad-v1-fk ciphertext" width="400"/> |
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+ | ascad-v1-fk | plaintext | 0 | <img src="plots/ascad_v1_fk_plaintext_0.png" alt="ascad-v1-fk plaintext" width="400"/> |
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+ | ascad-v1-fk | sbi | 0 | <img src="plots/ascad_v1_fk_sbi_0.png" alt="ascad-v1-fk sbi" width="400"/> |
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+ | ascad-v1-fk | sbo | 0 | <img src="plots/ascad_v1_fk_sbo_0.png" alt="ascad-v1-fk sbo" width="400"/> |
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+ | ascad-v1-fk | mask | 2 | <img src="plots/ascad_v1_fk_mask_2.png" alt="ascad-v1-fk mask" width="400"/> |
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+ | ascad-v1-fk | rin | none | <img src="plots/ascad_v1_fk_rin.png" alt="ascad-v1-fk rin" width="400"/> |
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+ | ascad-v1-fk | rout | none | <img src="plots/ascad_v1_fk_rout.png" alt="ascad-v1-fk rout" width="400"/> |
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  ## Parameters Used for Generation
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  - **HF_ORG**: `DLSCA`