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b/Wave2SVA-Benchmark-figures/Wave2SVA_Human_9.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0a1734a93a3eb879ea8aeef4810393a60928c23c10fd2ebd727306c6515ed138 +size 126414 diff --git a/Wave2SVA-Benchmark.jsonl b/Wave2SVA-Benchmark.jsonl new file mode 100644 index 0000000000000000000000000000000000000000..74ac10baa6e97280e5c96ed10689688049ad06e8 --- /dev/null +++ b/Wave2SVA-Benchmark.jsonl @@ -0,0 +1,50 @@ +{"name": "Wave2SVA_Human_0", "source": "assertllm/apbi2c_spec", "ground_truth": "asrt: assert property (@(posedge PCLK) (!PWRITE && PSEL && !PENABLE) |=> (PENABLE && PREADY) );", "clock": "PCLK", "signal_list": "PWRITE, PSEL, PENABLE, PREADY", "testbench": "module testbench (\n input PCLK,\n input PWRITE,\n input PSEL,\n input PENABLE,\n input PREADY\n);\nendmodule", "problem": "In a read protocol, if PWRITE is low, PSEL is high, and PENABLE is low in the current cycle, then PENABLE and PREADY must both be high in the next cycle."} +{"name": "Wave2SVA_Human_1", "source": "assertllm/i2c", "ground_truth": "asrt: assert property (@(posedge CLK) $rose(SDA) |-> !SCL ##1 (SCL && SDA) ##1 (SCL && !SDA) );", "clock": "CLK", "signal_list": "SDA, SCL", "testbench": "module testbench (\n input CLK,\n input SDA,\n input SCL\n);\nendmodule", "problem": "The clock signal is CLK. In the Repeat Start phase, if the SDA signal transitions from low to high, the SCL must be guaranteed to remain at a low level during the current cycle, and then transition to a high level in the next cycle while SDA maintains a high level in the next cycle. In the cycle after that, SDA must transition to a low level while SCL remains at a high level."} +{"name": "Wave2SVA_Human_2", "source": "assertllm/mac", "ground_truth": "asrt: assert property (@(posedge wb_clk_i) (wb_we_i && !wb_ack_o) |=> wb_we_i );", "clock": "wb_clk_i", "signal_list": "wb_we_i, wb_ack_o", "testbench": "module testbench (\n input wb_clk_i,\n input wb_we_i,\n input wb_ack_o\n);\nendmodule", "problem": "In the Wishbone interface, once the enable signal wb_we_i goes high, it must remain high until wb_ack_o becomes high."} +{"name": "Wave2SVA_Human_3", "source": "assertllm/openMSP430", "ground_truth": "asrt: assert property (@(posedge MCLK) DMA_READY |-> ##1 (DMA_DOUT == $past(DMA_DIN)) );", "clock": "MCLK", "signal_list": "DMA_READY, [15:0] DMA_DIN, [15:0] DMA_DOUT", "testbench": "module testbench (\n input MCLK,\n input DMA_READY,\n input [15:0] DMA_DIN,\n input [15:0] DMA_DOUT\n);\nendmodule", "problem": "If DMA_READY is high, then the DMA_DOUT of the next cycle will be the same as the DMA_DIN of the current cycle."} +{"name": "Wave2SVA_Human_4", "source": "other/avalon", "ground_truth": "asrt: assert property (\n @(posedge clk) \n read |-> ##[1:$] readdatavalid\n);", "clock": "clk", "signal_list": "read, readdatavalid", "testbench": "module testbench (\n input clk,\n input read,\n input readdatavalid\n);\nendmodule", "problem": "If the read signal is high in a certain clock cycle, then the readdatavalid signal must become high in some cycle after the current cycle."} +{"name": "Wave2SVA_Human_5", "source": "assertllm/lxp32", "ground_truth": "assert property ( @(posedge clk_i) (lli_re_o && !lli_busy_i) |-> ##1 (!$isunknown(lli_dat_i) || lli_busy_i) );", "clock": "clk_i", "signal_list": "lli_re_o, lli_busy_i, [31:0] lli_dat_i", "testbench": "module testbench (\n input clk_i,\n input lli_re_o,\n input lli_busy_i,\n input [31:0] lli_dat_i\n);\nendmodule", "problem": "When the lli_re_o signal is high and the lli_busy_i signal is low in the same cycle, the lli_busy_i signal must be asserted in the next cycle to indicate that the data is not yet ready."} +{"name": "Wave2SVA_Human_6", "source": "assertllm/lxp32", "ground_truth": "asrt: assert property (\n @(posedge clk_i) \n (dbus_cyc_o && dbus_stb_o) |-> dbus_ack_i\n);", "clock": "clk_i", "signal_list": "dbus_cyc_o, dbus_stb_o, dbus_ack_i", "testbench": "module testbench (\n input clk_i,\n input dbus_cyc_o,\n input dbus_stb_o,\n input dbus_ack_i\n);\nendmodule", "problem": "If in a certain cycle both dbus_cyc_o and dbus_stb_o are high, then dbus_ack_i is also high at the same cycle."} +{"name": "Wave2SVA_Human_7", "source": "assertllm/neo430", "ground_truth": "asrt: assert property (\n @(posedge CLK) \n RDEN |=> $changed(DI)\n);", "clock": "CLK", "signal_list": "RDEN, [15:0] DI", "testbench": "module testbench (\n input CLK,\n input RDEN,\n input [15:0] DI\n);\nendmodule", "problem": "In a read operation, when RDEN is active, DI must change in the next cycle."} +{"name": "Wave2SVA_Human_8", "source": "assertllm/openMSP430", "ground_truth": "asrt: assert property (\n @(posedge MCLK) \n $rose(DMA_PRIORITY) |-> ##1 (DMA_READY && (CPU_STATUS == OFF))\n);", "clock": "MCLK", "signal_list": "OFF, DMA_PRIORITY, DMA_READY, CPU_STATUS", "testbench": "module testbench (\n input MCLK,\n input DMA_PRIORITY,\n input DMA_READY,\n input CPU_STATUS\n);\n parameter OFF = 1'b0;\nendmodule", "problem": "If DMA_PRIORITY changes from low level to high level, the DMA_READY signal in the next cycle should also be at a high level and the CPU_STATUS signal should be OFF."} +{"name": "Wave2SVA_Human_9", "source": "assertllm/openMSP430", "ground_truth": "asrt: assert property (\n @(posedge mclk) \n $rose(irq[8]) |-> ##[1:$] (irq_acc[13:0] != 0)\n);", "clock": "mclk", "signal_list": "[15:0] irq, [15:0] irq_acc", "testbench": "module testbench (\n input mclk,\n input [15:0] irq,\n input [15:0] irq_acc\n);\nendmodule", "problem": "In a certain cycle after the 8th bit of irq becomes high level, the lower 14 bits of irq_acc must contain the response bits."} +{"name": "Wave2SVA_Human_10", "source": "assertllm/sha3", "ground_truth": "asrt: assert property (\n @(posedge clk) \n (buffer_full && in_ready) |-> ##1 (in == $past(in))\n);", "clock": "clk", "signal_list": "buffer_full, in_ready, [15:0] in", "testbench": "module testbench (\n input clk,\n input buffer_full,\n input in_ready,\n input [15:0] in\n);\nendmodule", "problem": "When both buffer_full and in_ready are at a high level, the in signal remains unchanged."} +{"name": "Wave2SVA_Human_11", "source": "assertllm/sdr_ctrl", "ground_truth": "asrt: assert property (\n @(posedge sdram_clk) \n (!app_wr_en_n && $rose(app_wr_next_req) ##1 !app_wr_next_req) |-> (app_wr_data != $past(app_wr_data))\n);", "clock": "sdram_clk", "signal_list": "app_wr_next_req, [31:0] app_wr_data, [3:0] app_wr_en_n", "testbench": "module testbench (\n input sdram_clk,\n input app_wr_next_req,\n input [31:0] app_wr_data,\n input [3:0] app_wr_en_n\n);\nendmodule", "problem": "The app_wr_data changes in the next cycle after the app_wr_en_n is enabled and the app_wr_next_req generates a pulse."} +{"name": "Wave2SVA_Human_12", "source": "openc906/XuanTie C906 Integration Manual", "ground_truth": "assert property ( @(posedge Cpu_clk) $rose(Sysclk) |-> Sysclk[*2] ##1 !Sysclk[*2] );", "clock": "Cpu_clk", "signal_list": "Sysclk", "testbench": "module testbench (\n input Cpu_clk,\n input Sysclk\n);\nendmodule", "problem": "Sysclk is a 4:1 frequency division of Cpu_clk, meaning one cycle of Sysclk is equivalent to four cycles of Cpu_clk, with a duty cycle of 50%."} +{"name": "Wave2SVA_Human_13", "source": "Loongson/Loongson 1C101 Processor User Manual", "ground_truth": "assert property ( @(posedge SCK) $fell(CSn) |-> !SDO ##1 !SDO ##1 !SDO ##1 !SDO ##1 SDO ##1 !SDO ##1 SDO ##1 SDO ##1 ##24 (!SDO)[*8] );", "clock": "SCK", "signal_list": "CSn, SDO", "testbench": "module testbench (\n input SCK,\n input CSn,\n input SDO\n);\nendmodule", "problem": "In the SPI Flash fast-read timing, when CSn transitions from high to low, the following 8 cycles of SDO form the command 0B (MSB first). After skipping the next 24 cycles, the following 8 cycles are a dummy byte."} +{"name": "Wave2SVA_Human_14", "source": "Loongson/Loongson 1C203 Processor User Manual", "ground_truth": "assert property ( @(posedge SCK) $fell(CSn) |-> SDO ##1 !SDO ##1 SDO ##1 SDO ##1 SDO ##1 !SDO ##1 SDO ##1 SDO );", "clock": "SCK", "signal_list": "CSn, SDO", "testbench": "module testbench (\n input SCK,\n input CSn,\n input SDO\n);\nendmodule", "problem": "In the SPI Flash dual-I/O read timing, when CSn transitions from high to low, the following 8 cycles of SDO form the command BB (MSB first)."} +{"name": "Wave2SVA_Human_15", "source": "Loongson/Loongson 2K0500 Processor User Manual", "ground_truth": "assert property ( @(posedge lioclk) (!liocs && liowr) |=> (addr[22:0] == $past(addr[22:0] + 1'b1)) );", "clock": "lioclk", "signal_list": "liocs, liowr, [31:0] addr", "testbench": "module testbench (\n input lioclk,\n input liocs,\n input liowr,\n input [31:0] addr\n);\nendmodule", "problem": "When liocs is low level and liowr is high level, the lower 23 bits of addr increment by 1 in the next cycle."} +{"name": "Wave2SVA_Human_16", "source": "XiangShan/WanZhongYiXin Verification Documentation Specification", "ground_truth": "assert property ( @(posedge clk) (!io_icacheInter_0_req_ready |=> $stable(io_icacheInter_0_req_bits_vaddr)) );", "clock": "clk", "signal_list": "io_icacheInter_0_req_ready, [31:0] io_icacheInter_0_req_bits_vaddr", "testbench": "module testbench (\n input clk,\n input io_icacheInter_0_req_ready,\n input [31:0] io_icacheInter_0_req_bits_vaddr\n);\nendmodule", "problem": "When io_icacheInter_0_req_ready is low, the io_icacheInter_0_req_bits_vaddr must remain unchanged in the next cycle."} +{"name": "Wave2SVA_Human_17", "source": "XiangShan/WanZhongYiXin Verification Documentation Specification", "ground_truth": "assert property (@(posedge clk) $rose(io_ftqInter_toFtq_pdWb_valid) |-> ##4 $rose(io_ftqInter_fromFtq_req_valid) ##1 $fell(io_ftqInter_fromFtq_req_ready) );", "clock": "clk", "signal_list": "io_ftqInter_toFtq_pdWb_valid, io_ftqInter_fromFtq_req_valid, io_ftqInter_fromFtq_req_ready", "testbench": "module testbench (\n input clk,\n input io_ftqInter_toFtq_pdWb_valid,\n input io_ftqInter_fromFtq_req_valid,\n input io_ftqInter_fromFtq_req_ready\n);\nendmodule", "problem": "Four cycles after io_ftqInter_toFtq_pdWb_valid becomes high, io_ftqInter_fromFtq_req_valid becomes high, followed by another cycle before io_ftqInter_fromFtq_req_ready becomes low."} +{"name": "Wave2SVA_Human_18", "source": "arm/AXI4", "ground_truth": "asrt: assert property (@(posedge ACLK) (TVALID && !TREADY) |=> $stable(INFORMATION) );", "clock": "ACLK", "signal_list": "TVALID, TREADY, [31:0] INFORMATION", "testbench": "module testbench (\n input ACLK,\n input TVALID,\n input TREADY,\n input [31:0] INFORMATION\n);\nendmodule", "problem": "Once the TVALID signal is high, the INFORMATION must remain unchanged in the next cycle until the slave pulls the TREADY signal high, indicating it can accept the data and control information."} +{"name": "Wave2SVA_Human_19", "source": "arm/AXI4", "ground_truth": "asrt: assert property (@(posedge ACLK) TVALID |=> $fell(TREADY) );", "clock": "ACLK", "signal_list": "TVALID, TREADY", "testbench": "module testbench (\n input ACLK,\n input TVALID,\n input TREADY\n);\nendmodule", "problem": "In the cycle following the valid TVALID signal, the TREADY signal changes from high level to low level."} +{"name": "Wave2SVA_Human_20", "source": "arm/AMBA", "ground_truth": "asrt: assert property (@(posedge ACLK) $rose(RREADY) |-> (##[0:$] (RLAST && RVALID && RRESP == Okay)) );", "clock": "ACLK", "signal_list": "RREADY, RLAST, RVALID, [1:0] Okay, [1:0] RRESP", "testbench": "module testbench (\n input ACLK,\n input RREADY,\n input RLAST,\n input RVALID,\n input [1:0] RRESP\n);\n parameter Okay = 2'b10;\nendmodule", "problem": "In the R channel, if RREADY transitions from low to high, the RLAST signal will eventually become high, and at that clock cycle, RVALID will also be high, while RRESP is Okay."} +{"name": "Wave2SVA_Human_21", "source": "arm/AHB", "ground_truth": "asrt: assert property (@(posedge HCLK) (HRESP == ERROR && $past(HRESP) == OKAY) |-> !HREADY ##1 (HRESP == ERROR && HREADY && HTRANS == IDLE) );", "clock": "HCLK", "signal_list": "HREADY, [1:0] HRESP, [1:0] HTRANS, [1:0] ERROR, [1:0] OKAY, [1:0] IDLE", "testbench": "module testbench (\n input HCLK,\n input HREADY,\n input [1:0] HRESP,\n input [1:0] HTRANS\n);\n parameter [1:0] ERROR = 2'b01;\n parameter [1:0] OKAY = 2'b00;\n parameter [1:0] IDLE = 2'b00;\nendmodule", "problem": "If in a certain cycle HRESP changes from OKAY to ERROR, then the HREADY of that cycle needs to be low, simultaneously in the next cycle HRESP must also remain ERROR, and HREADY must be pulled high, while ensuring HTRANS is IDLE."} +{"name": "Wave2SVA_Human_22", "source": "arm/AHB", "ground_truth": "assert property (@(posedge HCLK) \n (HREADY && HTRANS == NONSEQ && HBURST == WRAP8 && HSIZE == Word)\n |=> (HREADY && HTRANS == SEQ &&\n HBURST == WRAP8 &&\n HSIZE == Word)[*7]\n);", "clock": "HCLK", "signal_list": "HREADY, [1:0] HTRANS, [2:0] HBURST, [2:0] HSIZE, [1:0] NONSEQ, [1:0] SEQ, [2:0] WRAP8, [2:0] Word", "testbench": "module testbench #() (\n input HCLK,\n input HREADY,\n input [1:0] HTRANS,\n input [2:0] HBURST,\n input [2:0] HSIZE\n);\n parameter [1:0] IDLE = 2'b00;\n parameter [1:0] BUSY = 2'b01;\n parameter [1:0] NONSEQ = 2'b10;\n parameter [1:0] SEQ = 2'b11;\n parameter [2:0] WRAP8 = 3'b011;\n parameter [2:0] Word = 3'b010;\nendmodule", "problem": "If in a certain cycle HTRANS is NONSEQ, HBURST is WRAP8, HSIZE is Word, and HREADY is high, it indicates entry into the WRAP8 transfer phase. For the subsequent 7 cycles, HREADY must remain high, HTRANS must be SEQ, and the values of HBURST and HSIZE must remain unchanged."} +{"name": "Wave2SVA_Human_23", "source": "riscv/Wishbone", "ground_truth": "assert property (@(posedge HCLK) $rose(CYC_O) |-> (CYC_O throughout $rose(ACK_I)[->1]) ##1 !CYC_O );", "clock": "HCLK", "signal_list": "CYC_O, STB_O, ACK_I", "testbench": "module testbench (\n input HCLK,\n input CYC_O,\n input STB_O,\n input ACK_I\n);\nendmodule", "problem": "When CYC_O transitions from low level to high level, the transmission begins, and it must be kept at high level until ACK_I transitions from low level to high level, after which CYC_O should be set to low level in the next cycle."} +{"name": "Wave2SVA_Human_24", "source": "riscv/OBI", "ground_truth": "assert property (@(posedge clk) req && !gnt |=> $stable(addr) );", "clock": "clk", "signal_list": "req, gnt, [31:0] addr", "testbench": "module testbench (\n input clk,\n input req,\n input gnt,\n input [31:0] addr\n);\nendmodule", "problem": "If the req signal is high and the gnt signal is low, then the addr signal must remain unchanged in the next cycle."} +{"name": "Wave2SVA_Human_25", "source": "other/axi", "ground_truth": "asrt: assert property ( @(posedge ACLK) $rose(RLAST) |-> ##1 (!RACK && !AC && !CR) ##1 (RACK && !AC && !CR) ##1 (!RACK && !AC && !CR) ##1 (!RACK && AC && !CR) ##1 (!RACK && !AC && !CR) ##1 (!RACK && !AC && CR) );", "clock": "ACLK", "signal_list": "RLAST, RACK, AC, CR", "problem": "After the RLAST signal transitions from low to high, every other extra idle cycle (all three signals are low), RACK, AC, and CR produce a pulse signal in sequence.", "testbench": "module testbench (\n input ACLK,\n input RLAST,\n input RACK,\n input AC,\n input CR\n);\nendmodule"} +{"name": "Wave2SVA_Human_26", "source": "other/axi", "ground_truth": "asrt: assert property (@(posedge ACLK) CR |-> ##1 ((!RACK && !RLAST)[*0:$] ##1 (!RACK && RLAST)) ##1 (RACK));", "clock": "ACLK", "signal_list": "RLAST, RACK, AC, CR", "problem": "When CR is high, the transfer begins after one cycle. At this point, RACK must remain low until the next cycle after RLAST goes high, at which point RACK goes high.", "testbench": "module testbench (\n input ACLK,\n input AR,\n input RLAST,\n input RACK,\n input AC,\n input CR\n);\nendmodule"} +{"name": "Wave2SVA_Human_27", "source": "other/axi", "ground_truth": "asrt: assert property (@(posedge ACLK) SYSCOACK == $past(SYSCOREQ));", "clock": "ACLK", "signal_list": "SYSCOREQ, SYSCOACK", "problem": "The SYSCOACK signal lags one cycle behind the SYSCOREQ signal.", "testbench": "module testbench (\n input ACLK,\n input SYSCOREQ,\n input SYSCOACK\n);\nendmodule"} +{"name": "Wave2SVA_Human_28", "source": "other/axi-H", "ground_truth": "asrt: assert property (@(posedge ACLK) VALID == $past(CRDT));", "clock": "ACLK", "signal_list": "CRDT, VALID", "problem": "The VALID signal lags one cycle behind the CRDT signal.", "testbench": "module testbench (\n input ACLK,\n input CRDT,\n input VALID\n);\nendmodule"} +{"name": "Wave2SVA_Human_29", "source": "other/axi-H", "ground_truth": "asrt: assert property (@(posedge ACLK) (SHAREDCRD && VALID) |-> (RP == $past(RP)));", "clock": "ACLK", "signal_list": "VALID, SHAREDCRD, [1:0] RP", "problem": "When both SHAREDCRD and VALID are high, the RP signal must remain the same as the previous cycle's value.", "testbench": "module testbench (\n input ACLK,\n input VALID,\n input SHAREDCRD,\n input [1:0] RP\n);\nendmodule"} +{"name": "Wave2SVA_Human_30", "source": "other/axi-H", "ground_truth": "asrt: assert property (@(posedge ACLK) AWVALID |-> ##[0:$] ((AWRP == WRP) && WVALID));", "clock": "ACLK", "signal_list": "AWVALID, WVALID, [1:0] AWRP, [1:0] WRP", "problem": "When AWVALID is high, the value of AWRP will eventually equals to WRP at least once, and when they are equivalent, WVALID must be high.", "testbench": "module testbench (\n input ACLK,\n input AWVALID,\n input WVALID,\n input [1:0] AWRP,\n input [1:0] WRP\n);\nendmodule"} +{"name": "Wave2SVA_Human_31", "source": "other/axi-H", "ground_truth": "asrt: assert property (@(posedge ACLK) (State == RUN && ARCRDT) |-> ( (##17 (State == DEACT) ##2 (State == STOP && !ACTIVATEACK)) and ACTIVATEACK[*19] ) );", "clock": "ACLK", "signal_list": "State, ACTIVATEREQ, ACTIVATEACK, ASKSTOP, ARCRDT, ARVALID, RCRDT, RVALID, [1:0] STOP, [1:0] RUN, [1:0] DEACT", "problem": "When State is RUN and ARCRDT is high, State shall transition to DEACT after 17 clock cycles and then transition to STOP 2 cycles later. Throughout these cycles, ACTIVATEACK must remain high, and it must be deasserted (pulled low) when State reaches STOP.", "testbench": "module testbench (\n input ACLK,\n input [2:0] State,\n input ACTIVATEREQ,\n input ACTIVATEACK,\n input ASKSTOP,\n input ARCRDT,\n input ARVALID,\n input RCRDT,\n input RVALID\n);\n parameter [1:0] STOP = 2'b00;\n parameter [1:0] RUN = 2'b01;\n parameter [1:0] DEACT = 2'b10;\nendmodule"} +{"name": "Wave2SVA_Human_32", "source": "other/spi", "ground_truth": "asrt: assert property (@(posedge clk) ( !CONF_DONE && !INIT_DONE && ((Configuration_State == Idle) || (Configuration_State == Err)) ) |-> !nSTATUS);", "clock": "clk", "signal_list": "nSTATUS, CONF_DONE, INIT_DONE, [3:0] Configuration_State, [3:0] Idle, [3:0] Err", "problem": "Clock signal is clk. When Configuration_State is Idle or Err, and both CONF_DONE and INIT_DONE are low, nSTATUS is low.", "testbench": "module testbench (\n input clk,\n input nSTATUS,\n input CONF_DONE,\n input INIT_DONE,\n input [3:0] Configuration_State\n);\n parameter [3:0] Idle = 2'b00;\n parameter [3:0] Err = 2'b01;\nendmodule"} +{"name": "Wave2SVA_Human_33", "source": "other/intel_ip", "ground_truth": "asrt: assert property (@(posedge clk) (rxfifo_usedw == 3'b111) |-> rxfifo_almostfull);", "clock": "clk", "signal_list": "rxfifo_almostfull, [2:0] rxfifo_usedw", "problem": "When all bits of rxfifo_usedw are 1, rxfifo_almostfull is high.", "testbench": "module testbench (\n input clk,\n input rxfifo_almostfull,\n input [2:0] rxfifo_usedw\n);\nendmodule"} +{"name": "Wave2SVA_Human_34", "source": "other/intel_ip", "ground_truth": "asrt: assert property (@(posedge clk) (rxfifo_almostfull && got_new_char) |-> ##1 (rxfifo_almostfull && rxfifo_full && rxfifo_usedw == 3'b000));", "clock": "clk", "signal_list": "got_new_char, rxfifo_almostfull, rxfifo_full, [2:0] rxfifo_usedw", "problem": "When both rxfifo_almostfull and got_new_char are high, the next cycle must ensure that rxfifo_almostfull and rxfifo_full are both high, and rxfifo_usedw is low.", "testbench": "module testbench (\n input clk,\n input got_new_char,\n input rxfifo_almostfull,\n input rxfifo_full,\n input [2:0] rxfifo_usedw\n);\nendmodule"} +{"name": "Wave2SVA_Human_35", "source": "other/intel_ip", "ground_truth": "asrt: assert property (@(posedge clock_clk) (st_source_valid && !st_source_ready) |=> (st_source_data == $past(st_source_data)));", "clock": "clock_clk", "signal_list": "st_source_valid, st_source_ready, [7:0] st_source_data", "problem": "When st_source_valid is active but the related signal indicates that data is not yet ready, st_source_data remains unchanged for one cycle.", "testbench": "module testbench (\n input clock_clk,\n input st_source_empty,\n input st_source_sop,\n input st_source_eop,\n input st_source_valid,\n input st_source_ready,\n input [7:0] st_source_data\n);\nendmodule"} +{"name": "Wave2SVA_Human_36", "source": "other/intel_ip", "ground_truth": "asrt: assert property (@(posedge clk) (s1_awvalid && s1_awready) |-> ##[0:$] (s1_wlast && s1_wvalid && s1_wready));", "clock": "clk", "signal_list": "s1_awvalid, s1_awready, s1_wlast, s1_wvalid, s1_wready", "problem": "If s1_awvalid and s1_awready are simultaneously high, then after some number of cycles there must be a cycle where s1_wlast, s1_wvalid, and s1_wready are all high at the same time.", "testbench": "module testbench (\n input clk,\n input s1_awvalid,\n input s1_awready,\n input s1_wvalid,\n input s1_wready,\n input s1_wlast,\n input s1_bvalid,\n input s1_bready);\nendmodule"} +{"name": "Wave2SVA_Human_37", "source": "other/AHB", "ground_truth": "asrt: assert property (@(posedge HCLK) (HTRANS == NONSEQ && HWRITE) |-> ##1 (HWDATA == $past(HRDATA)));", "clock": "HCLK", "signal_list": "HWRITE, [1:0] HTRANS, [31:0] HRDATA, [31:0] HWDATA, [1:0] NONSEQ, [1:0] SEQ", "problem": "When HTRANS is NONSEQ and HWRITE is high, the HWDATA of the next cycle is the same as the HRDATA of the current cycle.", "testbench": "module testbench (\n input HCLK,\n input HWRITE,\n input HMASTLOCK,\n input [1:0] HTRANS,\n input [31:0] HADDR,\n input [31:0] HRDATA,\n input [31:0] HWDATA\n);\n parameter [1:0] NONSEQ = 2'b00;\n parameter [1:0] SEQ = 2'b01;\nendmodule"} +{"name": "Wave2SVA_Human_38", "source": "other/AHB", "ground_truth": "asrt: assert property (@(posedge HCLK) !HREADY |-> ##1 ((HTRANS == $past(HTRANS)) && (HADDR == $past(HADDR))));", "clock": "HCLK", "signal_list": "HREADY, [1:0] HTRANS, [31:0] HADDR, [1:0] NONSEQ, [1:0] SEQ", "problem": "When HREADY is low, the next cycle's HTRANS and HADDR should remain unchanged.", "testbench": "module testbench (\n input HCLK,\n input HWRITE,\n input HREADY,\n input [1:0] HTRANS,\n input [2:0] HBURST,\n input [2:0] HSIZE,\n input [3:0] HPROT,\n input [31:0] HADDR,\n input [31:0] HRDATA\n);\n parameter [1:0] NONSEQ = 2'b00;\n parameter [1:0] SEQ = 2'b01;\nendmodule"} +{"name": "Wave2SVA_Human_39", "source": "other/AHB", "ground_truth": "asrt: assert property (@(posedge HCLK) HBURST == SINGLE |=> ((HTRANS == IDLE || HTRANS == NONSEQ) && !HREADY) [*0:$] ##1 ((HTRANS == IDLE || HTRANS == NONSEQ) && HREADY) ##1 HTRANS == SEQ );", "clock": "HCLK", "signal_list": "HREADY, [1:0] HTRANS, [2:0] HBURST, [1:0] IDLE, [1:0] SEQ, [1:0] NONSEQ, [2:0] SINGLE", "problem": "When HBURST is SINGLE, starting from the next cycle HTRANS must remain IDLE or NONSEQ until HREADY goes high, and the next cycle after that it becomes SEQ.", "testbench": "module testbench (\n input HCLK,\n input HREADY,\n input [1:0] HTRANS,\n input [2:0] HBURST,\n input [31:0] HADDR,\n input [31:0] HRDATA\n);\n parameter [1:0] IDLE = 2'b00;\n parameter [1:0] SEQ = 2'b01;\n parameter [1:0] NONSEQ = 2'b10;\n parameter [2:0] SINGLE = 3'b010;\nendmodule"} +{"name": "Wave2SVA_Human_40", "source": "other/APB", "ground_truth": "asrt: assert property (@(posedge PCLK) (!PWRITE && PSEL && PENABLE) |-> ##[0:$] (PREADY && PSLVERR));", "clock": "PCLK", "signal_list": "PWRITE, PSEL, PENABLE, PREADY, PSLVERR", "problem": "When PWRITE is low and both PSEL and PENABLE are high, after some number of cycles both PREADY and PSLVERR will eventually become high.", "testbench": "module testbench (\n input PCLK,\n input PWRITE,\n input PSEL,\n input PENABLE,\n input PREADY,\n input PSLVERR\n);\nendmodule"} +{"name": "Wave2SVA_Human_41", "source": "other/wishbone", "ground_truth": "asrt: assert property (@(posedge CLK_I) STB_O |-> (STB_O until_with ACK_I));", "clock": "CLK_I", "signal_list": "STB_O, ACK_I", "problem": "STB_O must remain high until after ACK_I becomes high.", "testbench": "module testbench (\n input CLK_I,\n input STB_O,\n input ACK_I\n);\nendmodule"} +{"name": "Wave2SVA_Human_42", "source": "other/wishbone", "ground_truth": "asrt: assert property (@(posedge CLK_I) (CTI_O == 3'b000 && ADR_O == VALID && SEL_O == VALID && STB_O) |-> (ACK_I == (DAT_I == VALID)) );", "clock": "CLK_I", "signal_list": "SEL_O, STB_O, ACK_I, DAT_I, ADR_O, VALID, [2:0] CTI_O", "problem": "If CTI_O is 0, ADR_O and SEL_O are both VALID, and STB_O is high, then ACK_I is high if and only if DAT_I is VALID.", "testbench": "module testbench (\n input CLK_I,\n input SEL_O,\n input STB_O,\n input ACK_I,\n input DAT_I,\n input ADR_O,\n input [2:0] CTI_O);\n parameter VALID = 1'b1;\n parameter INVALID = 1'b0;\nendmodule"} +{"name": "Wave2SVA_Human_43", "source": "other/wishbone", "ground_truth": "asrt: assert property (@(posedge CLK_I) ($past(CTI_O) == 3'b010 && CTI_O == 3'b111) |-> (ADR_O == $past(ADR_O) + 4));", "clock": "CLK_I", "signal_list": "[2:0] CTI_O, [31:0] ADR_O", "problem": "When CTI_O changes from 010 to 111, ADR_O increases by 4 relative to the previous cycle.", "testbench": "module testbench (\n input CLK_I,\n input [2:0] CTI_O,\n input [31:0] ADR_O\n);\nendmodule"} +{"name": "Wave2SVA_Human_44", "source": "other/DDR4", "ground_truth": "asrt: assert property (@(posedge CK) (Command == Read) |-> ##2 (DQS ##1 !DQS ##1 DQS ##1 !DQS));", "clock": "CK", "signal_list": "[2:0] Read, [2:0] NOP, [2:0] Command, DQS", "problem": "Clock signal is CK. When Command is Read, after two cycles, the DQS produces two consecutive pulse signals.", "testbench": "module testbench (\n input CK,\n input [2:0] Command,\n input DQS\n);\n parameter [2:0] Read = 3'b001;\n parameter [2:0] NOP = 3'b000;\nendmodule"} +{"name": "Wave2SVA_Human_45", "source": "other/DDR4", "ground_truth": "asrt: assert property ( @(posedge CK) (Command == Write) |-> ##1 (Command == NOP)[*3] ##1 (Command == PRE) ##1 (Command == NOP) );", "clock": "CK", "signal_list": "[2:0] NOP, [2:0] PRE, [2:0] Write, [2:0] Command", "problem": "Clock signal is CK. When Command is Write, the next 3 cycles of Command are all NOP, then the following cycle is PRE, and the final cycle is still NOP.", "testbench": "module testbench (\n input CK,\n input [2:0] Command\n);\n parameter [2:0] Read = 3'b001;\n parameter [2:0] NOP = 3'b000;\n parameter [2:0] PRE = 3'b010;\n parameter [2:0] Write = 3'b011;\nendmodule"} +{"name": "Wave2SVA_Human_46", "source": "other/DDR4", "ground_truth": "asrt: assert property (@(posedge CK) (CKE && Command == NOP) |-> ##200 (Command == VALID));", "clock": "CK", "signal_list": "CKE, [2:0] NOP, [2:0] VALID, [2:0] Command", "problem": "Clock signal is CK. When CKE is high and Command is NOP, after 200 cycles Command becomes VALID.", "testbench": "module testbench (\n input CK,\n input CKE,\n input [2:0] Command\n);\n parameter [2:0] NOP = 3'b000;\n parameter [2:0] VALID = 3'b111;\nendmodule"} +{"name": "Wave2SVA_Human_47", "source": "other/spi_2", "ground_truth": "asrt: assert property (@(posedge SCK) !SC |-> ($onehot(SI) && (SI == $past(SI, 8))) );", "clock": "SCK", "signal_list": "SC, [7:0] SI", "problem": "When the SC signal is low, there is only one '1' in the bits of SI and it repeats every 8 cycles.", "testbench": "module testbench (\n input SCK,\n input SC,\n input [7:0] SI\n);\nendmodule"} +{"name": "Wave2SVA_Human_48", "source": "other/wishbone", "ground_truth": "asrt: assert property (@(posedge CLK_I) ($past(CTI_O) != 3'b010 && CTI_O == 3'b010) |-> ##3 (($past(ADR_O, 1) > ADR_O) && ($past(ADR_O, 2) == ADR_O + 8) && ($past(ADR_O, 3) == ADR_O + 8)) );", "clock": "CLK_I", "signal_list": "[2:0] CTI_O, [31:0] ADR_O", "problem": "When CTI_O changes to 010, ADR_O is constrained over the next 4 cycles as follows: assuming the start of the last cycle is N, the second-to-last cycle must start with a value greater than N, and the third-to-last and fourth-to-last cycles must both start with N + 8.", "testbench": "module testbench (\n input CLK_I,\n input [2:0] CTI_O,\n input [31:0] ADR_O\n);\nendmodule"} +{"name": "Wave2SVA_Human_49", "source": "other/AHB", "ground_truth": "asrt: assert property (@(posedge HCLK) ($past(HBURST) != INCR4 && HBURST == INCR4) |-> ((##1 ($stable(HADDR))[*2] ##1 (HADDR == $past(HADDR) + 4)) and (((HTRANS == NONSEQ)[*3]) ##1 (HTRANS == SEQ)) ) );", "clock": "HCLK", "signal_list": "[2:0] INCR4, [1:0] NONSEQ, [1:0] SEQ, [1:0] HTRANS, [2:0] HBURST, [31:0] HADDR", "problem": "When HBURST changes to INCR4, HADDR must remain unchanged for 3 cycles, increase by 4 in the 4th cycle, and HTRANS must be NONSEQ for the first 3 cycles and SEQ in the 4th cycle.", "testbench": "module testbench (\n input HCLK,\n input HREADY,\n input [1:0] HTRANS,\n input [2:0] HBURST,\n input [31:0] HADDR\n);\n parameter [2:0] INCR4 = 3'b100; parameter [1:0] NONSEQ = 2'b01; parameter [1:0] SEQ = 2'b10;\nendmodule"}