---
license: apache-2.0
---

# CodeV-SVA-VL: Automated Hardware Assertion Generation from Natural Language Specifications and Waveform Diagrams

<div align="center"> 
  <a href="https://huggingface.co/wyt2000/CodeV-SVA-14B"><img src="https://img.shields.io/static/v1?label=Model&message=HuggingFace&color=yellow"></a> &ensp;
  <a href="https://github.com/wyt2000/CodeV-SVA"><img src="https://img.shields.io/static/v1?label=Code&message=Github&color=blue"></a> &ensp;
</div>

## Introduction

We introduce Wave2SVA, a multimodal benchmark for evaluating large language models on SystemVerilog Assertion (SVA) generation from waveform diagrams and natural-language properties.

Open-Source Plan:

- Benchmark ✓
- Model 
- Evaluation code
- Paper
- Data synthesis and training code

## Benchmark 

The benchmark consists of the following files:

- `Wave2SVA-Benchmark.jsonl`: The main dataset where each entry contains:
  - `name`: Unique identifier of the assertion case.
  - `source`: Origin of the verification property (e.g., `assertllm/apbi2c_spec`).
  - `problem`: Natural-language description of the property in English.
  - `ground_truth`: The reference SystemVerilog Assertion (SVA).
  - `clock`: Clock signal used in the assertion.
  - `signal_list`: Comma-separated list of signals involved in the assertion.
  - `testbench`: A minimal testbench module declaring the relevant signals.
- `Wave2SVA-Benchmark-figures/`: Directory containing the corresponding waveform images for each case.