5_2_5_6_10-1-1011011000 — PyG power-electronics graphs (scratch build)

Scratch-sampled DC–DC converter designs simulated with ngSpice and packaged as PyTorch Geometric Data objects with:

• sparse switching-window V/I for all 31 nodes (V_sw, I_sw, T_sw ≈ 828), and
• full load-resistor R0 waveforms (V_r0_full, I_r0_full, T_full ≈ 12,250).

Unlike 5_4_3_6_10-1-1100111100, this dataset does not inherit rows from EngiBench IDEALLab/power_electronics_v0; designs are generated locally via grid_minmax, random, and latin_hypercube sampling.

Build environment: macOS, ngSpice (Homebrew / PATH), float32 tensors, parallel build (cpu_count-1 workers, NGSPICE_TIMEOUT=25, MAX_RETRIES=1 timeout-only). Simulation notebook: notebooks/examples/5_2_5_6_10-1-1011011000_scratch_macos.ipynb in the Dataset_Creation repository.

Topology

Bipartite PyG graph: 31 nodes (20 components + 11 port nets), 40 undirected edges (edge_index [2, 80] stores both orientations for message passing). Node colors: R=blue, L=green, C=red, D=yellow, V=orange, S=purple, ports=gray. Layouts: spring PNG / PDF, bipartite PNG / PDF.

Item	Value
Netlist	5_2_5_6_10-dcdc_converter_1.net
Switches / diodes / inductors / capacitors	5 S / 2 D / 5 L / 6 C
Fixed gate pattern	SWITCH_L1 = [1,0,1,1,0], SWITCH_L2 = [1,1,0,0,0] → 1011011000
Graph nodes	31 (20 components + 11 port nets)
Edges	40 undirected (bipartite); edge_index [2, 80] (both orientations)

Training with PyG

Each graph is an undirected bipartite circuit (40 unique edges). edge_index has shape [2, 80] because every undirected edge is stored in both orientations for message passing.

When training GNNs, pass data.edge_index as-is to PyG layers — use all 80 entries. Do not deduplicate to 40 edges; that would make the graph effectively directed unless you add custom handling.

Design source

Scratch build (USE_HF_SOURCE=False). Three sampling methods each contribute 18,432 designs (grid_minmax, random, latin_hypercube on a 2^6 × 2^5 × 9 continuous grid over C, L, and T1 duty), concatenated to 55,296 rows, shuffled once (SHUFFLE_SEED=523), then split 7:2:1.

Continuous ranges: C ∈ [1e-6, 2e-5], L ∈ [1e-6, 1e-3], T1 duty ∈ [0.1, 0.9]. Fixed gate binaries from SWITCH_L1 / SWITCH_L2 are appended to every design vector.

initial_design is [22] = 6 capacitances + 5 inductances + normalized T1 duty + 5× GS_L1 + 5× GS_L2.

Splits

split	graphs
train	38,707
val	11,059
test	5,530
total	55,296

Repository layout (this Hub dataset)

graphs/
├── train.pt              # list[Data], len 38707  (~14.5 GB)
├── val.pt                # list[Data], len 11059  (~4.1 GB)
├── test.pt               # list[Data], len 5530   (~2.1 GB)
└── large_ripple.json     # per-split indices with large_ripple = 1
circuit_topology_spring.png     # spring layout (600 DPI)
circuit_topology_spring.pdf
circuit_topology_bipartite.png  # bipartite layout (600 DPI)
circuit_topology_bipartite.pdf
level0_metric_success_tree.png  # metric_success decision tree
level0_metric_success_tree.pdf
simulation_success_tree.png     # simulation_success decision tree
simulation_success_tree.pdf
metric_success.md               # canonical metric_success doc
simulation_success.md           # canonical simulation_success doc
README.md                       # this dataset card

Total on-disk size ~20.7 GB (float32, pickle deduplication of shared topology inside each split file).

Measured wall time (macOS parallel build, Jul 2026): 1h 44m (train 1h 13m, val 21m 14s, test 10m 24s; ~0.11 s/sample effective).

outcome	count
simulation_success = 1	55,280
simulation_success = 0	16
ngspice_run_success = 0 (timeouts / infra)	0
metric_success = 0 with ngspice_run_success = 1 (nan_gain)	16
zero_gain_nan_ripple	0
positive_gain_nan_ripple	0
large_ripple = 1 (RIPPLE_CAP = 500)	30 (train 19, val 7, test 4)

Failure indices (simulation_success = 0): train 4461, 8901, 12525, 13709, 19225, 19748, 28526, 31993, 34691, 36471, 36553; val 42, 5545, 9905; test 1066, 1743.

All stored DcGain / Voltage_Ripple values on graphs are non-negative (abs of ngSpice log when finite). Manifest: graphs/large_ripple.json (only JSON under graphs/).

Use int(g.simulation_success) as the primary training filter — 99.97% of graphs pass in this build. In this rebuild, every metric_success = 1 sample also has waveform_success = 1 (55,280 / 55,280).

Load example

import torch
from huggingface_hub import hf_hub_download

repo_id = "LiangXD/5_2_5_6_10-1-1011011000"
path = hf_hub_download(repo_id, filename="graphs/train.pt", repo_type="dataset")
graphs = torch.load(path, weights_only=False)

g = graphs[153]
print(g.split, g.sample_index)           # 'train', 153
print(float(g.DcGain), int(g.large_ripple), int(g.zero_dc_gain))
if int(g.simulation_success):
    print(g.V_sw.shape)                  # torch.Size([31, 828])
    print(g.V_r0_full.shape)             # torch.Size([~12250])

torch.load reads an entire split file into RAM (~14.5 GB for train.pt). For random access at scale, repack or shard locally.

Data schema (per graph)

Waveforms

field	shape	description
V_sw, I_sw	[31, T_sw]	all nodes at sparse switching events (T_sw ≈ 828)
time_steps_sw	[T_sw]	time axis for switching windows
sw_indices	[T_sw]	indices into full grid
V_r0_full, I_r0_full	[T_full]	full R0 waveforms for QA
time_steps_full	[T_full]	full time axis
sw_pre_n, sw_post_n	scalar	window widths (30 / 5)

Labels and design

field	shape	description
DcGain	scalar	from ngSpice .meas log; abs() applied when finite
Voltage_Ripple	scalar	from ngSpice .meas log; abs() applied when finite
zero_dc_gain	scalar	1 iff |DcGain| ≤ 1e-6 on raw log; else 0
large_ripple	scalar	1 iff stored Voltage_Ripple > 500 (RIPPLE_CAP); else 0
initial_design	[22]	C, L, T1 duty, gate binaries
switching_parameters	[11]	[T1_duty, GS0_L1..GS4_L1, GS0_L2..GS4_L2]
ngspice_run_success	scalar	1 iff exit 0 and no timeout
waveform_success	scalar or omitted	Branch A; omitted when ngspice_run_success=0
metric_success	scalar or omitted	Branch B; omitted when ngspice_run_success=0
simulation_success	scalar	1 iff all three branch flags are 1

metric_success: stored on Data when ngspice_run_success=1 (0 or 1); omitted when ngSpice infra fails. Redundant with DcGain / Voltage_Ripple but attached for direct filtering.

Metric source. DcGain and Voltage_Ripple are read from ngSpice's .log file (.meas output), not recomputed from waveforms at build time. Cross-checked against V_r0_full in the build notebook (section 6: 2 samples; section 6b: 1 sample).

zero_dc_gain tolerance: DC_GAIN_ZERO_TOL = 1e-6. Rare case: |DcGain| ≤ tol with finite ripple → simulation_success = 1, zero_dc_gain = 1.

large_ripple: RIPPLE_CAP = 500 on stored Voltage_Ripple. Flags extreme ripple regardless of zero_dc_gain or gain magnitude (tol-zero, prints as 0.0000 in build logs, or normal e.g. 0.003). Does not set simulation_success = 0. Index manifest: graphs/large_ripple.json.

metric_success = 0 categories (section 7 stdout; aligns with Level-0 tree):

category	condition	count (this build)
nan_gain	DcGain NaN (ripple NaN)	16
zero_gain_nan_ripple	|DcGain| ≤ tol and ripple NaN	0
positive_gain_nan_ripple	|DcGain| > tol, gain finite, ripple NaN	0

Waveforms vs metrics. Branch A and Branch B are independent. V_r0_full / V_sw are present whenever .raw parses successfully — even when metric_success = 0. Metrics are read from .log on exit 0 even when .raw is missing or corrupt (finite DcGain / Voltage_Ripple may then coexist with simulation_success = 0). Waveforms omitted only on a Branch A failure (timeout, bad exit, missing/unparseable .raw, empty time series).

metric_success decision tree

Canonical reference: metric_success.md · PDF

Counts in the tree figure are from the Level-0 March 2022 raw dataset (illustration only; not this build).

Rule: metric_success = 1 iff isfinite(DcGain) AND isfinite(Voltage_Ripple) (Level-0 / Branch B only).

simulation_success decision tree

Canonical reference: simulation_success.md · PDF

Rule: simulation_success = 1 only if every PASS path below is reached. Any FAIL → simulation_success = 0.

Functions (call order): run_ngspice() → on exit 0, independent Branch A (rawread() from .raw) and Branch B (process_log_file() + classify_log_metrics() from .log) → merged in build_pyg_graph() as waveform_success AND metric_success (each branch requires ngspice_run_success=1).

PyG omit rule: PyG cannot store None. When ngspice_run_success=0, metric_success and waveform_success are omitted from Data (logs print =omitted). Waveform tensors (V_sw, …) use the same omit pattern.

Truth table (simulation_success):

ngspice_run_success	waveform_success	metric_success	simulation_success
0	omitted	omitted	0
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	1

Magnitude does not block success

Log value	Extra flag	Blocks simulation_success?
|DcGain| ≤ 1e-6	zero_dc_gain = 1	No (if ripple is finite)
|DcGain| > 1e-6	zero_dc_gain = 0	No
|Voltage_Ripple| > 500	large_ripple = 1	No

Finite near-zero gain and very large ripple can both coexist with simulation_success = 1.

---

Side flags (never flip simulation_success by themselves)

simulation_success = 1  AND  finite metrics
│
├─ |DcGain| ≤ DC_GAIN_ZERO_TOL (1e-6)
│    └─ zero_dc_gain = 1
│
└─ |Voltage_Ripple| > RIPPLE_CAP (500)
     └─ large_ripple = 1

---

One-line summary

simulation_success = 1 means ngSpice finished cleanly (ngspice_run_success=1), Branch A (waveform_success=1) and Branch B (metric_success=1) — regardless of whether gain is near-zero or ripple is very large.

---

Compact boolean form

ngspice_run_success = (exit == 0) AND (no timeout)

waveform_success =
    ngspice_run_success
    AND (raw_file_exists)
    AND (rawread_ok)
    AND (t_full > 0 AND t_sw > 0)

metric_success =
    ngspice_run_success
    AND isfinite(DcGain) AND isfinite(Voltage_Ripple)

simulation_success =
    ngspice_run_success
    AND (waveform_success == 1)
    AND (metric_success == 1)

When metric_success = 0, topology + rewrite_netlist_str remain; stored metrics keep abs(log) when finite; waveforms remain when .raw parsed. When Branch A (waveforms) fails but Branch B (metrics) succeeds, metrics may still be finite while simulation_success = 0. Use int(g.simulation_success) as the primary training filter.

Topology (shared across all graphs in this dataset)

field	description
edge_index	[2, 80] undirected COO (40 edges; both orientations stored)
node_name	list[str] — component/port names
node_type, bipartite, input_feature	per-node metadata

Bookkeeping

field	description
split	'train', 'val', or 'test'
sample_index	0-based index within split
rewrite_netlist_str	full ngSpice netlist text for this sample
raw_file	archived .raw basename (if built with archiving on)

Switching windows

• Switching period Ts = 5 µs (200 kHz). Transient window 1.0 ms → 1.06 ms (12 periods).
• 23 sparse events: T1+T2 for periods 0–10, period-11 T1 only (period-11 T2 omitted at t_stop).
• 36 steps per event: 30 before anchor + anchor + 5 after (SW_PRE_N / SW_POST_N).

Duty cycle

T1_duty in initial_design and switching_parameters[0] is the normalized duty in [0.1, 0.9]. Netlist on-time: GS{i}_T1 = T1_duty × 5e-6 seconds.

Ports vs components

• Component rows: V_sw = voltage across the device; I_sw = branch current.
• Port rows: V_sw = node voltage; I_sw = NaN.

Citation and license

This dataset: built with the Dataset_Creation pipeline (notebooks/examples/5_2_5_6_10-1-1011011000_scratch_macos.ipynb).